(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to the use of and a method of using PECVD boron carbide as an etch-stop and barrier layer for copper dual damascene metallization.
(2) Description of the Related Art
Copper dual damascene process is a well-known technique for forming interconnections in semiconductor devices. It is especially well suited for Ultra Large Scale Integrated (ULSI) circuit technology where more and more devices are being packed into the same or smaller areas in a semiconductor substrate. As the feature sizes get smaller, the smaller geometries result in higher electrical resistances, which in turn degrade circuit performance. As will be described more fully later, damascene process provides a more exact dimensional control over small geometries, while copper, as the metallization material, provides better electrical characteristics. It is disclosed in the present invention the use of, and a method of using, PECVD boron carbide as an etch-stop and barrier layer in a copper dual damascene structure in order to improve the performance of integrated circuit (IC) device.
The term xe2x80x98damascenexe2x80x99 is derived from a form of inlaid metal jewelry first seen in the city of Damascus. In the context of integrated circuits it implies a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. Thus, in semiconductor manufacturing, grooves and holes in appropriate locations in the grooves are formed in an insulating material by etching, which are then filled with metal. Metal in grooves form the horizontal metal line interconnects while the metal in the underlying holes form the vertical connections to the layers of metal interconnects formed in the previous damascene structure.
Thus, in a single damascene semiconductor manufacturing process, incisions, or grooves, are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the grooves of a single damascene, hole openings are also formed at appropriate places in the groove further into the insulating layer. The resulting composite structure of grooves and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed therebetween.
In one approach for a dual damascene process shown in FIG. 1a, two insulating layers (120) and (130) are formed on a substrate (100) with an intervening etch-stop layer (125). A desired trench or groove pattern (150) is first etched into the upper insulating material (130) using conventional photolithographic methods and photoresist (140). The etching stops on etch-stop layer (125). Next, a second photoresist layer (160) is formed over the substrate, thus filling the groove opening (150), and patterned with hole opening (170), as shown in FIG. 1b. The hole pattern is then etched into the lower insulating layer (120) as shown in FIG. 1c and photoresist removed, thus forming the dual damascene structure shown in FIG. 1f. 
Or, the order in which the groove and the hole are formed can be reversed. Thus, the upper insulating layer (130) is first etched, or patterned, with hole (170), as shown in FIG. 1d. The hole pattern is also formed into etch-stop layer (125). Then, the upper layer is etched to form groove (150) while at the same time the etching transfers the hole pattern in the etch-stop layer into lower insulation layer (120), as shown in FIG. 1e. It will be noted that the etch-stop layer stops the etching of the groove into the lower insulation layer. After the completion of the thusly formed dual damascene structure, both the hole opening and groove opening are filled with metal (180), and any excess material on the surface of the substrate is removed by chemical mechanical polishing, as seen in FIG. 1f. 
The metal that is commonly used as the damascene interconnect is aluminum because of its refined properties for etchability, as will be known to those skilled in the art. However, since copper has better electromigration property and lower resistivity than aluminum, it is a more preferred material for wiring than aluminum. By the same token, copper unfortunately suffers from high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. For instance, copper tends to diffuse into polyimide during high temperature processing of the polyimide. This causes severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. The corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required. It is disclosed later in the embodiments of the present invention that PECVD boron carbide or tantalum nitride is a preferred diffusion barrier layer.
It is also disclosed in the present invention that boron carbide is preferred as an etch-stop layer for its lower dielectric constant. Conventionally, silicon nitride (SiN) is used as a etch-stop layer. However, PECVD silicon nitride tends to be nonstoichiometric, while LPCVD nitride exhibits high tensile stresses, causing cracks for films greater that about 2000 xc3x85. Silicon nitride also exhibits outgassing which result in voids and, therefore, reliability problems. Furthermore, etch rates for silicon nitride are relatively fast so that for relatively low selectivity of silicon nitride to oxides in general, nitride layers must be thick. This results in cracks. More importantly, silicon nitride has a dielectric constant of about 7. It is desirable to use materials with lower dielectric constants as etch-stop layers, because they become a composite part of the interconnect, and hence affect the effective dielectric constant of the total composite structure, which affects the electrical characteristics of the device.
In prior art, a method for forming interconnections for semiconductor fabrication and semiconductor devices are described. In U.S. Pat. 5,817,572, Chiang, et al., a first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filled with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material The first patterned dielectric layer serves as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer is formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer serves as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of die dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.
In another U.S. Pat. No. 5,658,834, Dowben describes active semiconductor devices including heterojunction diodes and thin film transistors, which are formed by PECVD deposition of a boron carbide thin film on an N-type substrata. The boron to carbon ratio of the deposited material is controlled so that the film has a suitable band gap energy. The stoichiometry of the film can be selected by varying the partial pressure of precursor gases, such as nido pentaborane and methane.
Summerfelt, in U.S. Pat. No. 5,851,896, on the other hand, shows a conductive exotic-nitride barrier layer for high-dielectric-constant material electrodes. An embodiment of this invention comprises an oxidizable layer (e.g. TiN), a conductive exotic-nitride barrier layer (e.g. Tixe2x80x94Alxe2x80x94N) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.
In still another U.S. Patent, Gnade, et al., disclose a different method of forming electrical connections to high dielectric constant materials. An embodiment of this invention comprises an oxidizable layer (e.g. tantalum), an oxygen gettering layer (e.g. platinum/tantalum mixture) overlaying the oxidizable layer, a noble metal layer (e.g. platinum) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate) overlaying the noble metal layer. The structures presented provide electrical connection to high-dielectric-constant. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. The invention provides a stable and electrically conductive electrode for high-dielectric-constant materials while using standard integrated circuit materials to facilitate and economize the manufacturing process.
In the present invention, a method of forming a boron carbide layer for use as a barrier and an etch-stop layer in a copper dual damascene structure, and the structure itself are disclosed.
It is therefore an object of this invention to provide a method of forming a copper dual damascene structure having a boron carbide etch-stop layer with a low dielectric constant.
It is another object of this invention to provide a method of forming a copper dual damascene structure having a boron carbide layer as a barrier to copper diffusion.
It is still another object of the present invention to provide a copper dual damascene structure having boron carbide layers with effective low dielectric constant, good copper diffusion barrier, good insulating properties and high etching selectivity with respect to insulating layers.
It is an over-all object of the present invention to provide a damascene structure wherein one or more of the passivation, etch-stop, and cap layer, or combination barrier and passivation layer are formed of boron carbide.
These objects are accomplished by providing a semiconductor substrate having a first conductive layer; forming a boron carbide (BC) passivation layer over said conductive layer; forming a first dielectric layer over said BC passivation layer; forming a BC etch-stop layer over said first dielectric layer; forming a second dielectric layer over said BC etch-stop layer; forming a BC cap layer over said second dielectric layer; forming a first photoresist layer over said cap layer and patterning said photoresist layer with a mask comprising a via hole pattern; etching through said via pattern in said first photoresist layer to form said via hole in said BC cap layer and said second dielectric layer until said BC etch-stop layer is reached; etching through said via hole pattern to form said via hole in said BC etch-stop layer; etching further said via hole pattern into said first dielectric layer until BC passivation layer is reached; removing said first photoresist layer; forming a second photoresist layer over said BC cap layer including said via hole in said second dielectric layer; patterning said second photoresist layer with a mask comprising a line trench pattern; etching through said line trench pattern in said second photoresist layer into said BC cap layer and said second dielectric layer and into said BC etch-stop layer; etching further through said hole pattern in said BC etch-stop layer and extending said hole pattern into said BC passivation layer thus forming a dual damascene structure comprising a composite hole and line trench pattern in said substrate; removing said second photoresist layer; forming a barrier lining on the inside walls of said dual damascene structure; forming metal over said barrier lining in said dual damascene structure; and forming a combination barrier and passivation layer over said substrate including over said dual damascene structure.
These objects are accomplished in a second embodiment providing a semiconductor substrate having a substructure comprising devices formed in said substrate and a conductive layer formed thereon; a boron carbide (BC) passivation layer over said conductive layer; a first dielectric layer over said first BC passivation layer; a BC etch-stop layer over said first dielectric layer; a second dielectric layer over said BC etch-stop layer; a BC cap layer over said second dielectric layer; a dual damascene structure having a top portion and inside walls formed within first and second dielectric layers; said dual damascene structure having a barrier layer lining said inside walls; and said dual damascene structure having a combination barrier and etch stop layer over said top portion.